Jobs · topdev

Senior/Leader Design Verification Engineer
FPT IS · Vietnam · Posted 30d ago
About the role
Develop and implement verification plans for SoC designs, focusing on testbench development and debugging. The role includes mentoring junior engineers and ensuring quality assurance in design verification.
Full job description (as posted) ↓
Responsibilities:
Verification Planning: Develop and implement verification plans aligned with SoC specifications. Testbench Development: Design scalable, reusable testbenches using SystemVerilog and UVM. Debugging and Analysis: Identify and resolve design and verification issues. Coverage and Quality Assurance: Drive functional and code coverage to meet project goals. Leadership: Mentor junior engineers and lead verification for IP blocks or subsystems. Automation: Utilize scripting languages (Python, Perl, Tcl) to enhance verification efficiency.
Requirements:
Bachelor's or Master's degree in Electrical Engineering or Electronic Engineering. Proven experience in SoC design verification, including unit and combine test strategies. Strong knowledge of AMBA protocols: AHB, APB, AXI (mandatory) and IPs Proficiency in verification methodologies such as SystemVerilog, UVM (preferred), and SVA. Familiarity with programming languages like Verilog, assembly, C/C++. Proven ability to communicate clearly and transparently with both internal teams and global customers. Capable of managing daily workflows and leading a design team with full ownership and accountability. Nice to have: Basic understanding of formal verification techniques and scripting using TCL, Python.
Benefits:
Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers: Competitive compensation package, aligned with capabilities and performance. Project bonuses when you join ODC (Offshore Development Center) projects Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation. Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices. Access to professional training and development programs within FPT Corporation. Working hours: 9:00 AM - 6:00 PM, Monday to Friday. Working location: Ho Chi Minh, Ha Noi
Read the full posting on topdev →
FAQ
Is the Senior/Leader Design Verification Engineer role at FPT IS remote?+
This Senior/Leader Design Verification Engineer position is listed as onsite (Vietnam).
What seniority level is this Senior/Leader Design Verification Engineer role?+
This is a senior level position.
How do I apply for the Senior/Leader Design Verification Engineer role at FPT IS?+
Use the "Apply on topdev" button to open the original posting on topdev, where you can submit your application directly to FPT IS.