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ML Research Engineer - Hardware Codesign
Keystone AI · San Francisco · Indexed today
About the role
Develop silicon and system-level solutions for advanced AI workloads.
ML Research Engineer - Hardware CodesignDepartment: ScalingLocation: San FranciscoCompensation: $185K – $455K • Offers EquityEmployment Type: FullTimeAbout the TeamKeystone AI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to de
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Why this role stands out
- ★Pays more than 95% of comparable ml roles paid in USD in United States
- ★Equity is part of the package
- ★Equity
Responsibilities
- ▸Develop next generation of AI silicon
- ▸Co-design hardware integrated with AI models
Benefits
- ▸Equity
FAQ
Is the ML Research Engineer - Hardware Codesign role at Keystone AI remote?+
This ML Research Engineer - Hardware Codesign position is listed as onsite (San Francisco).
What is the salary for the ML Research Engineer - Hardware Codesign role at Keystone AI?+
The listing states 179000-441000 USD.
What seniority level is this ML Research Engineer - Hardware Codesign role?+
This is a unknown level position.
How do I apply for the ML Research Engineer - Hardware Codesign role at Keystone AI?+
Use the "Apply on echojobs" button to open the original posting on echojobs, where you can submit your application directly to Keystone AI.