Jobs · greenhouse:asteralabs
A
Lead Logic Design - PCIE IP/Subsystem Engineer
Asteralabs · Bengaluru, Karnataka, India · Posted 5d ago
onsiteFull-timelead8+ yrs🇮🇳 India
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About the role
Lead the design and development of complex connectivity IPs and subsystems, focusing on RTL/microarchitecture development. Collaborate with verification teams and drive performance optimization while ensuring robust design practices.
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FAQ
Is the Lead Logic Design - PCIE IP/Subsystem Engineer role at Asteralabs remote?+
This Lead Logic Design - PCIE IP/Subsystem Engineer position is listed as onsite (Bengaluru, Karnataka, India).
What seniority level is this Lead Logic Design - PCIE IP/Subsystem Engineer role?+
This is a lead level position.
How do I apply for the Lead Logic Design - PCIE IP/Subsystem Engineer role at Asteralabs?+
Use the "Apply on greenhouse:asteralabs" button to open the original posting on greenhouse:asteralabs, where you can submit your application directly to Asteralabs.